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Research Article

Year : 2019 | Volume: 3 | Issue: 4 | Pages: 7-15

VLSI Arcitectures of Carry Skip Adders – A Survey

JOHN MOSES C1*, Bisam Pranaya2

doi:10.24951/sreyasijst.org/2019041002

Corresponding author

JOHN MOSES C*

Sreyas Institute of Engineering and Technology

  • 1. Sreyas Institute of Engineering and Technology

Received on: 1/6/2019

Revised on: 1/6/2019

Accepted on: 1/6/2019

Published on: 1/6/2019

Abstract

Adders are key building blocks in the arithmetic and logic units and hence increasing their speed and reducing their power consumption strongly affect the performance of digital circuits. There are many adder families with different delays, power consumptions, and area usages.  Carry skip adder (CSKA) is efficient in terms of power consumption and area usage; delay also smaller than the ripple carry adder (RCA). CSKA allows carry to skip over group of n bits. This paper analyses different very large scale integration (VLSI) design characteristics of various CSKAs in terms of area, power and speed. Based on the detailed review, this paper suggests that by using variable size on stages of skip logic, both delay and power can be improved. Further, this work suggests that for high performance implementation, multi-level with variable block size and and-or-invert (AOI) skip logic and multiplexer-based full adder blocks are preferred for reducing the required number of transistors.

Keywords

CMOS, VLSI, ALU, processors, transistors.